1. Field of the Invention
The present invention relates to memory controller architectures in computing systems. More specifically, the present invention relates to methods and structure for providing a flexible, pipelined read return control structure for high-performance memory subsystems shared by multiple processors.
2. Discussion of Related Art
In general, it is known in computing systems that a processor or master device fetches and stores data and instructions in an associated memory subsystem. Most present day system architectures include a memory controller device intermediate the master device and memory components. The memory controller device shields the processor from details of the architecture of the memory subsystem and control mechanisms of the memory subsystem. For example, details of a controlling row and column selection for RAM chips (i.e., RAS and CAS signals), refresh operations for dynamic RAM chips, bank selection and control in multibank memory subsystems, etc. are all relegated to methods and circuits operable within the memory controller device. The system processor is coupled directly to the memory controller device as are other xe2x80x9cmasterxe2x80x9d devices such as DMA controllers and intelligent I/O processors. The memory controller device therefore includes methods and logic circuits for interfacing to the processor bus structure as well as methods and logic for controlling the memory chips of the memory subsystem and serves as an intermediary or interface between the two.
The processor or other master device issues read requests to retrieve information previously stored in the memory subsystem. The memory controller device interacts with the processor and memory elements to perform the requested read. There are typically delays between the issuance of a read by the master device and the completion of the request by return of the requested data. A number of factors are involved in these delays including round trip signal times between the processor, memory controller and memory elements as well as factors relating to the memory chips themselves. For example, timing of addressing signals applied to memory chips often have latency times associated with them (i.e., CAS latency). A system designer must carefully evaluate these factors and appropriately design the system to account for such delays. It is desirable that the master device requesting the data be ready to receive the retrieved data when it becomes available. If the master device is ready to receive the data too early, it may stallxe2x80x94retaining control of the bus until the memory subsystem is ready to deliver the data to the master device. If the master is ready to receive the data too late, FIFO devices in the return path for read data may be held in use thereby delaying servicing of later read requests. Where a system has but a single master device coupled to the memory subsystem, these issues are less important and may be largely ignored by a designer.
It is also known in present architectures that multiple processors or masters may be coupled to a common or shared memory subsystem. In general, such architectures include a single memory controller device capable of interacting with multiple masters over a shared processor bus. In such systems having multiple master devices, it is desirable that each master issue its read request and then release the shared bus for other transactions while awaiting and preparing for return of the requested data. Such other transactions may include, for example, other read requests by other master devices. It is common therefore to provide read return control information prior to actual return of the requested data so that bus arbitration and control logic can determine which master device is to receive the read data about to be returned from the memory subsystem. Such read return control information may include, among other things, indicia of the requesting master device (i.e., a device ID or other indicia) and information indicative of completion of the requested read transaction. There are therefore latencies associated with return of the read return control information as well as the return of the actual requested data from the memory subsystem.
In such multiple processor systems, the design problems in accounting for these latencies in memory read transactions are multiplied and more critical to overall system performance. To achieve optimal performance of a system, a system designer must provide for accurate delays in the processing of read commands to memory and the return of the requested read information. These delay times vary in accordance with a number of factors in a system design as noted above and the problems that arise from inaccurate delays are exacerbated by contention issues that arise in the context of multiple masters.
In a system with multiple masters sharing the memory subsystem, bus contention problems arise when multiple masters require simultaneous access to the memory subsystem. Resolution of such contention problems can be a significant factor in the overall system performance of such a multiple master system. If one of the simultaneous requesting masters is delayed too long in retrieving its requested data, other read requests may be delayed because the read data return path (typically including a FIFO device) is controlled by the delayed processor. If the requesting processor is not delayed long enough, it could take ownership of the read control path too early thereby precluding other masters from legitimately commencing other operations in parallel. It is important in such multiprocessor system architectures to provide accurate timing for returning requested read data from a shared memory subsystem. As noted above, incorrect timing can cause undesired stalls of processors in a multiple processor system.
Present solutions to such performance issues require a designer to correctly design a fixed delay for return of read control information to masters on the shared bus. Specific timing requirements are unique to the specific application of the memory controller and include timing requirements relating to the bus coupling the masters to the memory controller. Such fixed delay designs are inflexible where different applications of the memory controller may vary the number, types or clock speeds of processors for particular applications or where the memory controller is to be used with other masters, buses and memory subsystems having different latencies.
It is evident from the above discussion that a need exists for improved flexibility in the design of memory controller devices in a shared memory subsystem shared by multiple processors.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing a programmable read return delay line signal path for multiple processor system designs incorporating a shared memory subsystem. More specifically, the present invention provides for a programmable delay line signal path to customize the delay in the return of read control information to any of the multiple masters in a system. This programmable delay allows the total delay time associated with a read operation to be flexibly tuned to the needs of a particular application of the memory controller (i.e., a particular bus and a particular compliment of master devices coupled through that bus to the memory controller). A register associated with the memory controller allows the user (designer) to program the specific delay used by the corresponding system application. The delay circuit is preferably programmed at system initialization to configure the appropriate delay length for this particular application of the memory controller.
Another aspect of the present invention provides for firmware operable within a processor master device (or other programmable master device) coupled to the memory controller to determine an optimal delay value for the programmable delay line in the return of read return control information. The optimal delay is determined by trying various delay values in the configuration register of the memory controller and measuring system performance at each setting attempted. The optimal value so determined may then be written to the delay line configuration register for use by the memory controller device in this particular application.
These features permit a memory controller to be easily adapted to a variety of bus applications without need for custom designing delay lines in each new application. Rather, the memory controller of the present invention is easily adapted to each new application environment.
A first aspect of the invention provides for a system for controlling access to a memory by a master device comprising: a programmable delay line signal path having an input signal path and an output signal path coupled to the master device; read return logic circuits associated with the memory and coupled to the input signal path of the programmable delay line signal path wherein read return control signals generated by the read return logic circuits are delayed by a programmable delay period and wherein the delayed read return control signals are applied through the output signal path of the programmable delay line signal path to the master device to control return of information read from the memory by the master device.
Another aspect provides further that the programmable delay line signal path comprises: a plurality of delay flip-flops coupled in a sequential manner such that the output signal from a preceding delay flip-flop is controllably applied to the input of a next delay flip-flop and such that the output of the last delay flip-flop in the sequence of delay flip-flops is applied as the output signal path of the programmable delay line signal path to the master device as delayed read return logic.
Another aspect provides further for a configuration register having a plurality of bits wherein each bit is associated with a corresponding delay flip-flop of the plurality of delay flip-flops such that the setting of the each bit controls the selective application of the read return control signals to the corresponding delay flip-flop.